Integrating VHDL compiler with Code::Blocks

[ahmed.shahein]

Dear All,

I am using Code:Blocks since a while to compile cpp and SystemC codes as well. However, recently I would like to compile VHDL codes within Code::Blocks as well, in order to have a complete design environment. I had VHDL compiler on Ubuntu, ghdl.

How can I add ghdl compiler to the compilers list of CBs?

In waiting for your support.

Regards.

[danselmi]

Hi

I do a lot VHDL at work.

What I use mostly are the following Tools+ entries:

Code Select Expand

##Tools Plus Plugin (v0.6) Command Export##
COMMAND#####################################
name:Compile VHDL file VHDL93 (ModelSim)
command line:C:\Modeltech\win32xoem\vcom -93 -explicit $file
workdir:c:\msimwork
wildcards:*.vhd;*.vhdl
menu string:Simulation/Compile file VHDL93 (ModelSim)
menu priority:100
context menu string:Simulation/Compile file VHDL93 (ModelSim)
context menu priority:100
envvarset:
mode (W,C,):W
COMMAND#####################################
name:Sim (ModelSim)
command line:C:\Modeltech\win32xoem\vsim $fname
workdir:c:\msimwork
wildcards:*.vhd;*.vhdl
menu string:Simulation/Simulate entity (ModelSim)
menu priority:100
context menu string:Simulation/Simulate entity (ModelSim)
context menu priority:100
envvarset:
mode (W,C,):

The drawback, the name of the entity to simulate (the testbench) must match the filename.

The other possibility: GHDL is able to generate makefiles which are easy to use from within codeblocks.

regards danselmi

[ahmed.shahein]

Thanks for your reply.

I am already using makefile but form the command line. The issue now that I am having bigger designs, i.e. 10's of VHDL files. Therefore, I was looking forward to have all of them in a signal project entry and to compile and debug them as well.

I have ghdl installed. Do you how to integrate it with Code::Blocks?

Regards.